The present invention relates generally to driver circuits and, more particularly, to a driver circuit including first and second opposite conductivity type transistors which are prevented from conducting simultaneously during a transition between first and second voltage levels by pulse shaping circuitry, and to a method of operating same.
One type of driver circuit that is frequently employed, particularly on integrated circuit chips, includes first and second opposite conductivity type transistors, each including a control electrode and a path which is switched on and off between a pair of further electrodes. Each path is switched on and off in response to a voltage applied to the control electrode of the particular transistor being on opposite sides of a threshold. The paths of the first and second transistors are connected in series across terminals of a DC power supply. An output terminal between the series connected paths drives a load.
In a typical integrated circuit chip, the transistors are opposite conductivity type metal oxide semiconductor field effect transistors (MOSFETs), wherein the control electrodes are gate electrodes and the further electrodes are source and drain electrodes. Such a driver includes a positive channel field effect transistor (PFET) and a negative channel field effect transistor (NFET). The switched path between the source and drain electrodes of each field effect transistor (FET) is frequently referred to as a source drain path and the source drain paths of the PFET and NFET are connected in series across opposite polarity terminals of the power supply.
The typical integrated circuit chip includes many such drivers that are responsive to bilevel sources having positive and negative going transitions between first and second voltage levels that are usually approximately equal to the voltages at the power supply terminals. The bilevel sources can be either data or clock sources. In response to the bilevel source being at the first (low) voltage level, the PFET and NFET are respectively on and off, while the NFET and PFET are respectively on and off in response to the bilevel source being at the second (high) voltage level. A relatively high impedance is provided by the source drain path of the NFET or PFET which is off so that substantial current does not flow through both the PFET and NFET of the driver while the bilevel source is at the first and second voltage levels. To minimize power consumption, the PFET and NFET should not be on at the same time during the transitions.
Many of the drivers of the foregoing type on a typical integrated circuit chip are simultaneously responsive to the transitions. If many of the drivers of the foregoing type are simultaneously responsive to the transitions and if the PFET and NFET of each of these drivers were on at the same time during the transitions, a substantial amount of current, frequently referred to as crow bar current, would be drawn from the power supply. The current could be so great as to cause overheating of the integrated circuit chip and result in a substantial decrease in the voltage between the power supply terminals. Similar problems can also exist with bipolar drivers including PNP and NPN transistors having series connected emitter collector paths.
In the past, one approach to resolving the problem has involved complicated circuitry which takes into account processing variables in making the integrated circuits, as well as changes that occur to the circuit elements as a result of power supply voltage and temperature variations of the integrated circuit chip carrying the circuitry. Another complicated approach has involved staging a number of field effect transistors. These complicated circuits occupy a significant amount of space on the integrated circuit chip and consume additional power, resulting in possible unnecessary heating of the chip.
There is a prior art circuit wherein conventional capacitors are connected in negative feedback paths to the gates of opposite conductivity type field effect transistors having series connected source drain paths. One electrode of each capacitor is connected to an output terminal between the source drain paths, while the other electrode of each capacitor is connected to the gate electrode of one of the field effect transistors. A problem with this approach is that the voltage across each of the capacitors varies as a function of load variations. Hence, switching of the field effect transistors is a function of the load variations which can result in poor control. In this prior art circuit, both field effect transistors appear to be turned on simultaneously during a transition, resulting in substantial current flow. Another problem with this prior art circuit is that the capacitors are charged and discharged through source drain paths of additional field effect transistors, rather than through resistors.
In accordance with one aspect of the invention, a circuit comprises an input terminal for connection to a voltage source having first and second levels and a transition between the levels, and a driver includes first and second opposite conductivity type transistors, each including a control electrode and a path switched on and off in response to the control electrode voltage being on opposite sides of a threshold. The first and second transistor paths are connected in series across opposite power supply terminals. Pulse shaping circuitry causes the first and second transistor paths to be respectively (1) on and off while the voltage source has the first level, and (2) off and on while the voltage source has the second level. The pulse shaping circuitry also prevents both paths from being on simultaneously. The circuitry includes a first resistive impedance and first shunt capacitor, wherein the first resistive impedance is connected for supplying current to the first capacitor and the first transistor control electrodes. The first capacitor is connected across the first transistor control electrode and a first of the power supply terminals.
Another aspect of the invention relates to a circuit comprising an input terminal for connection to a voltage source having first and second levels and a transition between the levels. A driver includes first and second opposite conductivity type transistors, each including a control electrode and a path switched on and off in response to a voltage applied to the control electrode being on opposite sides of a threshold. The first and second transistor paths are connected in series across opposite power supply terminals. Pulse shaping circuitry causes the paths of the first and second transistors to be respectively (1) on and off while the voltage source has the first level and (2) off and on while the voltage source has the second level. The pulse shaping circuitry also prevents the first and second transistors from being on simultaneously. The circuitry includes first and second switching circuits adapted to be connected to be simultaneously responsive to the voltage at the input terminal. The first and second switching circuits respectively include output terminals having DC connections to the control electrodes of the first and second transistors. The pulse shaping circuitry also has first and second capacitors respectively having DC connections between (1) the first control electrode and the first power supply terminal and (2) the second control electrode and the second power supply terminal.
The first switching circuit includes a first resistive impedance for supplying current from the first power supply terminal to the control electrode of the first transistor and the first capacitor while the voltage at the input terminal has the first level. The first switching circuit is arranged for supplying a voltage substantially equal to the voltage at the second power supply terminal to (1) the control electrode of the first transistor and (2) the first capacitor while the voltage at the input terminal has the second level.
The second switching circuit includes a second resistive impedance for supplying current from the second power supply terminal to the control electrode of the second transistor and the second capacitor while the voltage at the input terminal has the second level. The second switching circuit is arranged for supplying a voltage substantially equal to the voltage at the first power supply terminal to (1) the control electrode of the second transistor and (2) the second capacitor while the voltage at the input terminal has the first level.
In a preferred embodiment, the first switching circuit comprises a first inverter including third and fourth transistors respectively switched on and off in response to the voltage at the input terminal respectively having first and second values. The first inverter includes the first resistive impedance for supplying current from the first power supply terminal to the control electrode of the first transistor and the first capacitor while the third transistor is switched on. The second switching circuit comprises a second inverter including fifth and sixth transistors respectively switched on and off in response to the voltage at the input terminal respectively having first and second values. The second inverter includes the second resistive impedance for supplying current from the second power supply terminal to the control electrode of the second transistor and the second capacitor while the sixth transistor is switched on.
In the preferred embodiment, the fourth and fifth transistors while switched on are connected to supply voltages substantially at the second and first power supply terminals to the control electrodes of the first and second transistors and the first and second capacitors, respectively.
Another aspect of the invention relates to a method of operating a driver including first and second opposite conductivity type transistors, each including a control electrode and a path controlled in response to a voltage applied to the control electrode. The paths of the first and second transistors are connected in series across opposite power supply terminals. First and second capacitors are respectively connected in shunt with the control electrodes. During a first interval: the paths of the first and second transistors are respectively turned on and off, while the second capacitor is charged and the first capacitor is discharged by applying (1) a first voltage having a first value to the control electrode of the first transistor, (2) the first voltage value across the second capacitor, and (3) a second voltage having the first value to the control electrode of the second transistor. During a second interval: the paths of the first and second transistors are respectively turned off and on, while the second capacitor is discharged and the first capacitor is charged by applying (1) the second value of the first voltage to the control electrode of the first transistor, (2) the first voltage value across the first capacitor, and (3) the second value of the second voltage to the control electrode of the second transistor. During an initial portion of a first transitional period between the first and second intervals: the path of the first transistor is turned off while the path of the second transistor is maintained off by changing the first voltage from the first value toward the second value while the first capacitor remains substantially discharged and the second capacitor remains substantially charged. During a second portion of the first transitional period, the path of the second transistor is turned on while the path of the first transistor is maintained off by changing the charge on the second capacitor so that there is a change in the value of the second voltage from the first value toward the second value. During an initial portion of a second transitional period between the second and first intervals: the path of the second transistor is turned off while the path of the first transistor is maintained off by changing the second voltage from the second value toward the first value while the second capacitor remains substantially discharged and the first capacitor remains substantially charged. During a second portion of the second transitional period the path of the first transistor is turned on while the path of the second transistor is maintained off by changing the charge on the first capacitor so that there is a change in the value of the first voltage from the second value toward the first value.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of a specific embodiment thereof, especially when taken in conjunction with the accompanying drawings.